2023 |
32nd International Workshop on Logic & Synthesis June 5 – 6, 2023 EPFL, Lausanne, Switzerland
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Our sponsors
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| IWLS 2023 Technical Program |
| Jun. 4th | ||
| Pre-workshop Social Event: Vineyard Walk (Please enroll in your
registration form if you are interested). We are organizing a walk/light hike on Sunday, June 4, the day before the workshop through the Lavaux vineyards. This event is unofficially organized and possible public transportation costs are not covered by the official registration fee. Nevertheless, for organizational purposes, please indicate your interest in the registration form. Details can be found at the https://www.iwls.org/iwls2023/ |
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| Jun. 5th | ||
| 8:20 - 8:30: Opening Session | Opening Keynote - Cunxi Yu (Univ. of Utah), Lana Josipovic (ETH Zurich), Xiaoqing Xu (Google X) | |
| 8.30 - 9.30: Keynote | Robert Wille - Technical University of Munich, Germany (Session Chair: Cunxi Yu) | Design Automation for Quantum Computing: How to (Not) Re-invent the Wheel for an Emerging Technology |
| 9:30-10.30: Paper Session | Session 1 - Advancements in Technology Mapping (Session Chair: Alan Mishchenko) | |
| 21 | Dewmini Marakkalage (EPFL), Marcel Walter (TUM), Siang-Yun Lee (EPFL), Robert Wille (TUM) and Giovanni De Micheli (EPFL) | Technology Mapping for Beyond-CMOS Circuitry with Unconventional Cost Functions (Best student paper nominee) |
| 6 | Peiyu Wang, Anqi Lu (Shanghai Jiao Tong University), Xing Li, Junjie Ye, Lei Chen, Mingxuan Yuan, Jianye Hao (Huawei Noah's ark Lab) and Junchi Yan (Shanghai Jiao Tong University) | EasyMap: Improving Technology Mapping via Exploration-Enhanced Heuristics and Adaptive Sequencing |
| 22 | Hanyu Wang, Carmine Rizzi and Lana Josipović (ETH Zurich) | MapBuf: Simultaneous Technology Mapping and Buffer Insertion for HLS Performance Optimization |
| 10.30 - 10:50: Coffee Break | BC 420 | |
| 10:50 - 12:10: Paper Session | Session 2 - Advancements in Logic Synthesis (Session Chair: Xiaoqing Xu) | |
| 7 | Xing Li, Lei Chen (Huawei), Jiantang Zhang (Hisilicon), Weihua Sheng and Mingxuan Yuan (Huawei) | EffiSyn: Efficient Logic Synthesis with Dynamic Scoring and Pruning |
| 3 | Ruofei Tang, Xuliang Zhu (Hong Kong Baptist University), Lei Chen, Xing Li (Huawei Noah’s Ark Lab), Xin Huang (Hong Kong Baptist University), Mingxuan Yuan, Weihua Sheng (Huawei Noah’s Ark Lab) and Jianliang Xu (Hong Kong Baptist University) | Maximum Fanout-Free Window Enumeration: Towards the Local Multi-Output Sub-structure Synthesis (Best student paper nominee) |
| 5 | Yukio Miyasaka (UC Berkeley) | Transduction Method for AIG Minimization (Best student paper nominee) |
| 4 | Yingjie Li, Mingju Liu, Alan Mishchenko and Cunxi Yu (University of Utah) | DAG-Aware Synthesis Orchestration |
| 12.10 - 13.10: Lunch | EPFL | |
| 13.10 - 14.25: Special Session | Special Session 1 - Synthesis and Verification from an Industrial Perspective (Session Chair: Lana Josipović) | |
| Victor Kravets (IBM TJ Watson Research) | Formalization of synthesis tasks to improve chip design | |
| Attila Jurecska (Siemens EDA) | Data Path Verification Challenges in High-Level Verification | |
| Ankush Sood (Cadence) | Word level abstraction in synthesis and how it can improve “everything”! | |
| 14.25 - 15.10 Posters + Coffee | BC 420 | |
| Poster Presentation | 5 min presentation and live discussion afterwards (Session Chair: Stefan Nikolić) | |
| 15 | Victor M. van Santen (University of Stuttgart), Marcel Walter (TUM), Florian Klemme, Shivendra Singh Parihar (University of Stuttgart), Girish Pahwa (UC Berkley), Yogesh Chauhan (IIT Kanpur), Robert Wille and Hussam Amrouch (TUM) | Design Automation for Cryogenic CMOS Circuits |
| 19 | Hongyang Pan, Ruibing Zhang, Yinshui Xia, Lunyao Wang and Zhufei Chu (Ningbo University ) | Semi-Tensor Product based Circuit Simulation for SAT sweeping |
| 8 | Viktor Teren (Università degli Studi di Verona), Jordi Cortadella (Universitat Politecnica de Catalunya) and Tiziano Villa (Università degli Studi di Verona) | A framework for the decomposition of Petri nets and transition systems |
| 28 | Chandan Kumar Jha, Khushboo Qayyum, Kemal Çağlar Coşkun (University of Bremen), Simranjeet Singh (IIT Bombay), Muhammad Hassan (DFKI GmbH), Rainer Leupers (RWTH Aachen University), Farhad Merchant (Newcastle University) and Rolf Drechsler (University of Bremen) | Automated Formal Verification Methodology for MAGIC Design Style Based In-Memory Computing |
| 15.10 - 16.30: Paper Session | Session 3 - Advancements in Circuit Minimization and Simplification (Session Chair: Siang-Yun Lee) | |
| 26 | Franz Reichl, Friedrich Slivovsky and Stefan Szeider (TU Wien) | Circuit Minimization with Exact Synthesis: From QBF Back to SAT |
| 12 | Kuo-Wei Ho, Tian-Fu Chen, Shao-Ting Chung, Yu-Wei Fan, Che Cheng, Cheng-Han Liu and Jie-Hong Roland Jiang (National Taiwan University ) | WolFEx: Word-Level Function Extraction and Simplification from Gate-Level Arithmetic Circuits |
| 2 | Alessandro Tempia Calvino and Giovanni De Micheli (EPFL) | Technology Mapping Using Multi-output Library Cells |
| 13 | Alan Mishchenko, Robert Brayton (UC Berkeley) and Masahiro Fujita (University of Tokyo ) | Mapping and Retiming Revisited |
| 18:30 - 20:30 | Dinner (Café Romand - Brasserie et pinte depuis 1951, Pl. Saint-François 2, 1003 Lausanne, Switzerland) | |
| Jun. 6th | ||
| 8.30 - 9.30: Keynote | Patrick Vuillod – Synopsys, France (Session Chair: Giovanni De Micheli) | Advanced Logic Synthesis Techniques for High-Performance Industrial Circuit Design |
| 9.30 - 10.10: Paper Session | Session 4 - Logic Optimization (Session Chair: Winston Haaswijk) | |
| 20 | Sen Liu, Hongyang Pan, Yinshui Xia, Lunyao Wang and Zhufei Chu (Ningbo University) | Multiplicative Complexity Optimization Based on Boolean-Difference Resubstitution |
| 14 | Alan Mishchenko, Robert Brayton (UC Berkeley), Alessandro Tempia Calvino and Giovanni De Micheli (EPFL) | Boolean Decomposition Revisited |
| 10.10 - 10.40: Coffee Break | BC 420 | |
| 10.40 - 12.00: Paper Session | Session 5 - Emerging trends and technologies for synthesis (Session Chair: Christian Pilato) | |
| 16 | Simon Hofmann, Marcel Walter, Lorenzo Servadei and Robert Wille (TUM) | Thinking Outside the Clock: Physical Design for Field-coupled Nanocomputing with Deep Reinforcement Learning |
| 25 | Siang-Yun Lee (EPFL), Heinz Riener (Cadence) and Giovanni De Micheli (EPFL) | Customizable On-the-fly Design Space Exploration for Logic Optimization of Emerging Technologies |
| 10 | Bernhard Gstrein and Armin Biere (University of Freiburg) | Delirious Representations: Enhancing Predictive Systems with Flexible Numeric and Symbolic Domain Integration |
| 17 | Andrea Costamagna (EPFL), Alan Mishchenko (UC Berkeley) and Giovanni De Micheli (EPFL) | The Combinational-Complexity Game For Symmetric Functions |
| 12.00 - 13.30: Lunch | EPFL | |
| 13.30 - 14.45: Special Session | Special Session 2 - Synthesis for Hardware Security (Session Chair: Satrajit Chatterjee) | |
| Christian Pilato (Politecnico di Milano) | Enhancing Hardware Security and Trust with High-Level Design Methods | |
| Samuel Pagliarini (Tallinn University of Technology) | A Security-aware and LUT-based CAD Flow for the Physical Synthesis of hASICs | |
| Nima Kavand (TU Dresden) | Designing Secure Hardware Using Reconfigurable Field-Effect Transistors | |
| 14.45 - 15.15 Coffee Break | BC 420 | |
| 15.15 - 15.30 Benchmark Session | EPFL Benchmark Results Update Alessandro Tempia Calvino (EPFL, Switzerland) |
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| 15.30 - 16.10: Paper Session | Session 6 - Verification (Session Chair: Marcel Walter) | |
| 9 | Samuel Coward, Emiliano Morini, Bryan Tan, Theo Drane (Intel Corporation) and George Constantinides (Imperial College London) | Datapath Verification via Word-Level E-Graph Rewriting |
| 27 | Jiahui Xu and Lana Josipović (ETH Zurich) | Automatic Inductive Invariant Generation for Scalable Dataflow Circuit Verification |
| 16:10 - 16:50 | Paper and Contest Awards & Closing | |